Controlled ring oscillators are commonly used for Integrated Circuit (IC) applications where trigger and stop operations of the oscillator are required to be precisely monitored and controlled. FIG. 1 shows a conventional oscillator consisting of a ring of delay elements or inverters Td and a final control stage Cs, which enables/disables the ring. The control stage Cs has an inverter Tiv and a logic gate Tand.
The logic gate Tand receives the output of the inverter Tiv, an enabling/disabling signal ENABLE, and provides a clock output CLK_OUT. When the ring is enabled by the ENABLE signal, the CLK_OUT has an oscillating waveform. Thus the conventional circuit acts as a trigger start oscillator with a frequency Fclk=(1/(TTd+TTiv+TTand)*2), where TTd, TTivTTand are the delays. This type of oscillator produces glitches when disabled, which is a major problem.
The waveform in FIG. 2 shows an output of the conventional oscillator between two disable signals. When the ENABLE signal is set to disable the oscillator, the CLK_OUT goes to ‘0’ irrespective of the present value, which creates a problem of a minimum pulse width violation for the next stage, or results in a glitch that can have adverse effects on the next stage. This would generate an error of the order of ˜(1/Fclk) for a synchronous system. Further, the size of this glitch or pulse can vary at different process and voltage corners.
Thus, conventional methods not only have errors with regards to the output clock, but it is also difficult to estimate the error as the error has large process, voltage, and temperature dependence. This is very critical, particularly for on-chip integrated circuits where an accuracy of few picoseconds is desired and it is expected that the design should have minimal impact of process, voltage, and temperature variations.